Why can Moore's law continue? I can't believe it's packaging technology!
Internet of things, big data and AI technologies are putting forward new requirements on chip performance, power, area cost and time to market (ppact), which are beyond the scope of classical Moore's law. This has led to a new solution, one of the key technologies is advanced packaging, which is used to support heterogeneous design and integrate various similar or different chips. Designers can integrate CMOS chips of various node and wafer sizes with other functions, including power, RF and photonics. They can combine silicon wafers from different IDMS and fabs to heterogeneous chips, subsystems, or highly integrated systems. In short, it can bring design and manufacturing flexibility to a new level, thus solving the chip ppact.
Recently, an outstanding panel discussion was held at the IEEE International Conference on electronic devices (IEDM) in San Francisco, hosted by applied Regina free, and attended by experts from Facebook, IBM, Intel, Stanford University and TSMC. This article will focus on the group members' views on heterogeneous design and advanced packaging, and share some of Applied's ongoing innovative work in this field to help realize the logical progress in the next decade in the field of logic.
Team members discussed two industries that could benefit from advanced packaging: cloud computing and 5g. Supercomputing architects are looking for new ways to achieve higher performance at constant or low power consumption. 5g infrastructure and equipment designers also put signal integrity, size, heat dissipation, and cost first.
Heterogeneous design and advanced packaging provide new methods beyond 2D extension to achieve the optimization that engineers expect. Functional system blocks do not need to apply the latest nodes, and can be manufactured on mature nodes, which makes it possible to reuse existing logical designs. Reusing existing designs can reduce silicon costs, shorten design time, and speed up mass production and time to market, which is a key factor in establishing leadership in promising new markets. In addition, advanced packaging can be used to shorten chip interconnection and reduce parasitism, thus significantly improving data rate and overall performance.
"I firmly believe that advanced packaging technology will drive Moore's law," said Ramune nagisetty, senior chief engineer and director of process and product integration technology development group at Intel. The future is the scale specialization of advanced packaging and interoperable chips. I predict that an industry scale ecosystem will evolve around the concept of chiplet library, in which you can replace an old technology node with a new one, such as in a high-speed kernel. Then you can mix specific functions in specific nodes, such as power transmission, memory, or a specific type of accelerator (such as GPU). This is basically to bring the high division chip technology into the field of advanced packaging。
Applied's advanced packaging development center in Singapore is committed to enabling the industry to make breakthroughs in heterogeneous integration. The plant is one of the most advanced wafer packaging laboratories in the world, focusing on the development of wafer level system and process technology solutions to achieve the future roadmap of heterogeneous packaging integration.
They achieve this goal by implementing the basic "building blocks" of heterogeneous integration, namely advanced bump and micro bump (1D), thin wire redistribution layer (rdl-2d), silicon through channel (tsv-3d) and hybrid interconnection (hbi-3d). In addition to the unit level processes, applied and its partners are developing full process solutions for these building blocks, which are validated with internally designed testing tools.